Only sequential statements are allowed inside a process statement. An architecture statement part is comprised of zero or more concurrent statements. rtl appears to be the name of architecture and a process statement is a concurrent statement.
Notice from your referenced code you are having problems with:
That the line you ask about in your question is line 54:
And that this a concurrent signal assignment and yet it is showing up in a process statement (the domain of sequential statements).
The form of this is a 'conditional signal assignment', which happens to have been added to sequential signal assignments by IEEE Std 1076-2008 (10.5.3 Conditional signal assignments, § 10 is entitled Sequential statements).
And from this we can infer that while Modelsim supports the 2008 VHDL standard, your XST doesn't (error messages of the form 'ERROR:HDLParsers:' are XST messages).
If and when Xilinx would support synthesis of conditional signal assignment statements within a process (as sequential signal assignment) is a matter of versions and/or policy. There's no particular difference in difficulty of synthesis to support it, while representing significant change in the parser.
VHDL is case insensitive except in extended identifiers and character literals.
From IEEE Std 1076-2008 15.2 Character set:
The only characters allowed in the text of a VHDL description (except within comments—see 15.9, and within text treated specially due to the effect of tool directives—see 15.11) are the graphic characters and format effectors. Each graphic character corresponds to a unique code of the ISO eight-bit coded character set (ISO/IEC 8859-1:1998) and is represented (visually) by a graphical symbol.
upper_case_letter | digit | special_character | space_character
basic_graphic_character | lower_case_letter | other_special_character
basic_graphic_character | format_effector
The basic character set is sufficient for writing any description, other than a PSL declaration, a PSL directive, or a PSL verification unit.
And 15.4 Identifiers:
All characters of a basic identifier are significant, including any underline character inserted between a letter or digit and an adjacent letter or digit. Basic identifiers differing only in the use of corresponding uppercase and lowercase letters are considered the same.
Thanks a lot for the answer, how about the Inside_process vs Outside_process ? Out_signal <= signal1 and (not signal2); Out_signal is being assigned once inside and once outside, but the result doesn't change, circuit still works, no warnings? So is this a sequential assignment or concurrent? If concurrent, how can it be inside the process, if sequential, how can it be outside the process? – Anarkie 6 hours ago
There's an obvious difference between the two processes. The one with the concurrent signal assignment() will have show change immediately upon change update for signals and because the concurrent signal assignment will have an equivalent process containing a sequential signal assignment statement and a sensitivity list equivalent containing and . (Every signal appearing on the right hand side of a signal assignment statement).
The process only has in the sensitivity list, meaning in simulation will be assigned at the next , an apparent half clock delay because the assignments to your two shift register signals are visible in the next delta cycle.
See this stackoverflow answer The VHDL Simulation Cycle as well as this one - Unexpected delays with register VHDL.
Interestingly enough both will probably synthesize identically because the sensitivity list will either be disregarded or updated (assumed to include and in ). Any assumptions should likely show up in warnings.
Elaboration devolves a design description into block statements (maintaining hierarchy), process statements and function calls. All concurrent statements have a process statement equivalent, potentially within block statements (or nested block statements). In the case of simple signal assignment statements there is little observable difference between signal assignment inside or outside a process (except the sensitivity list which in this case is incomplete for ).
A design specification will be elaborated before simulation and as a predicate for synthesis as well.
A signal assignment statement modifies the projected output waveforms contained in the drivers of one or more signals
signal_name <= [delay_mechanism ] waveform ;
signal_name <= [delay_mechanism ] waveform1 when condition1 else
[delay_mechanism ] waveform2 when condition2 else
. . .
[delay_mechanism ] waveformn;
with selection select
signal_name <= [delay_mechanism ] waveform1 when choice1,
[delay_mechanism ] waveform2 when choice2,
. . .
[delay_mechanism ] waveformn when others;
Signal assignment statement can appear inside a process or directly in an architecture. Accordingly, sequential signal assignment statements and concurrent signal assignment statements can be distinguished. The latter can be divided into simple concurrent signal assignment, conditional signal assignment and selected signal assignment.
The target signal can be either a name (simple, selected, indexed, or slice) or an aggregate.
All signal assignments can be delayed. See delay for details.
Sequential signal assignment
If a sequential signal assignment appears inside a process, it takes effect when the process suspends. If there are more than one assignments to the same signal in a process before suspension, then only the last one is valid. Regardless of the number of assignments to a signal in a process, there is always only one driver for each signal in a process (Example 1).
If a signal is assigned a value in a process and the signal is on the sensitivity list of this process, then a change of the value of this signal may cause reactivation of the process (Example 2).
Concurrent signal assignment
The concurrent signal assignment statements can appear inside an architecture. Concurrent signal assignments are activated whenever any of the signals in the associated waveforms change their value. Activation of a concurrent signal assignment is independent from other statements in given architecture and is performed concurrently to other active statements (Example 3). If there are multiple assignments to the same signal then multiple drivers will be created for it. In such a case, the type of the signal must be of the resolved type (see resolution function).
Conditional signal assignment
Conditional signal assignment is a form of a concurrent signal assignment and plays the same role in architecture as the if then else construct inside processes. A signal is assigned a waveform if the Boolean condition supported after the when keyword is met. Otherwise, the next condition after the else clause is checked, etc. Conditions may overlap.
A conditional signal assignment must end with an unconditional else expression (Example 4).
Selected signal assignment
Selected signal assignment is a concurrent equivalent of a sequential case construct. All choices for the expression must be included, unless the others clause is used as the last choice (Example 5). Ranges and selections can be used as the choice (Example 6). It is not allowed for choices to overlap.
signal A, B, C, X, Y, Z : integer;
process (A, B, C)
X <= A + 1;
Y <= A * B;
Z <= C - X;
Y <= B;
When this process is executed, signal assignment statements are performed sequentially, but the second assignment (Y <= A * B) will never be executed because only the last assignment to Y will be activated. Moreover, in the assignment to Z only the previous value of X will be used as the A + 1 assignment will take place when the process suspends.
signal A, B, C, X, Y, Z : integer;
process (A, B, C)
X <= A + 1;
Y <= A * B;
Z <= C - X;
B <= Z * C;
When the process is activated by an event on the signal C this will cause change on the signal B inside a process, which will in turn reactivate the process because B is in its sensitivity list.
architecture Concurrent of HalfAdder is
Sum <= A xor B;
Carry <= A and B;
The above architecture specifies a half adder. Whenever A or B changes its value, both signal assignments will be activated concurrently and new values will be assigned to Sum and Carry.
architecture Conditional of TriStateBuffer is
BufOut <= BufIn when Enable = '1'
The architecture specifies a tri-state buffer. The buffer output BufOut will be assigned the value of buffer input BufIn only when the Enable input is active high. In all other cases the output will be assigned high impedance state.
architecture Concurrent of UniversalGate is
with Command select
DataOut <= InA and InB when "000",
InA or InB when "001",
InA nand InB when "010",
InA nor InB when "011",
InA xor InB when "100",
InA xnor InB when "101",
Architecture of UniversalGate is specified with a selected signal assignment. Depending on the value of the Command signal, the DataOut signal will be assigned value resulting from the logical operation of two inputs. If none of the specified codes appears, the output is set to high impedance.
with IntCommand select
MuxOut <= InA when 0 | 1,
InB when 2 to 5,
InC when 6,
InD when 7,
A specialized multiplexer is defined here with a selected signal assignment. Note that both range and selections can be used as a choice.
Signal assignment statements are generally synthesizeable but delays are usually ignored.
Choices in selected signal assignment are separated by colons.
All signal assignments can be labeled for improved readability.